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ISCAS
2007
IEEE
78views Hardware» more  ISCAS 2007»
15 years 3 months ago
Towards Automated Power Gating of Registers using CoDeL
— In this paper, we use the CoDeL platform to develop test circuits and analyze the potential and performance impact of power gating individual registers. For each register, we e...
Nainesh Agarwal, Nikitas J. Dimopoulos
ISCA
2007
IEEE
117views Hardware» more  ISCA 2007»
15 years 3 months ago
ReCycle: : pipeline adaptation to tolerate process variation
Process variation affects processor pipelines by making some stages slower and others faster, therefore exacerbating pipeline unbalance. This reduces the frequency attainable by t...
Abhishek Tiwari, Smruti R. Sarangi, Josep Torrella...
ISCA
2007
IEEE
192views Hardware» more  ISCA 2007»
15 years 3 months ago
Analysis of redundancy and application balance in the SPEC CPU2006 benchmark suite
The recently released SPEC CPU2006 benchmark suite is expected to be used by computer designers and computer architecture researchers for pre-silicon early design analysis. Partia...
Aashish Phansalkar, Ajay Joshi, Lizy Kurian John
ISCA
2007
IEEE
114views Hardware» more  ISCA 2007»
15 years 3 months ago
Matrix scheduler reloaded
From multiprocessor scale-up to cache sizes to the number of reorder-buffer entries, microarchitects wish to reap the benefits of more computing resources while staying within po...
Peter G. Sassone, Jeff Rupley, Edward Brekelbaum, ...
ISCAS
2007
IEEE
106views Hardware» more  ISCAS 2007»
15 years 3 months ago
Ensemble Dependent Matrix Methodology for Probabilistic-Based Fault-tolerant Nanoscale Circuit Design
—Two probabilistic-based models, namely the Ensemble-Dependent Matrix model [1][3] and the Markov Random Field model [2], have been proposed to deal with faults in nanoscale syst...
Huifei Rao, Jie Chen, Changhong Yu, Woon Tiong Ang...