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ISCAS
2007
IEEE
84views Hardware» more  ISCAS 2007»
15 years 3 months ago
High Speed 1-bit Bypass Adder Design for Low Precision Additions
—In this paper, we propose a high speed adder which is adopted for our reconfigurable architecture called FleXilicon. To support sub-word parallelism, the FleXilicon architecture...
Jong-Suk Lee, Dong Sam Ha
ISCAS
2007
IEEE
105views Hardware» more  ISCAS 2007»
15 years 3 months ago
Parallel current-steering D/A Converters for Flexibility and Smartness
—This paper presents a DAC architecture built on parallel current-steering sub-DAC entities. Two main novelties are explored: flexibility and smartness. Firstly, a number of avai...
Georgi I. Radulov, Patrick J. Quinn, Pieter Harpe,...
ISCAS
2007
IEEE
149views Hardware» more  ISCAS 2007»
15 years 3 months ago
Compact, Low Power Wireless Sensor Network System for Line Crossing Recognition
— Many application-specific wireless sensor network (WSN) systems require small size and low power features due to their limited resources, and their use in distributed, wireles...
Chung-Ching Shen, Roni Kupershtok, Bo Yang, Felice...
ISCAS
2007
IEEE
84views Hardware» more  ISCAS 2007»
15 years 3 months ago
System Bandwidth Analysis of Multiview Video Coding with Precedence Constraint
— Multiview video coding (MVC) systems require much more bandwidth and computational complexity relative to mono-view video systems. Thus, when designing a VLSI architecture for ...
Pei-Kuei Tsung, Li-Fu Ding, Wei-Yin Chen, Shao-Yi ...
ISCAS
2007
IEEE
96views Hardware» more  ISCAS 2007»
15 years 3 months ago
Novel High-Speed Redundant Binary to Binary converter using Prefix Networks
— Fast addition and multiplication are of paramount importance in many arithmetic circuits and processors. The use of redundant number system for efficient implementation of thes...
Sreehari Veeramachaneni, Kirthi M. Krishna, Lingam...