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ISCA
2007
IEEE
145views Hardware» more  ISCA 2007»
15 years 3 months ago
Mechanisms for store-wait-free multiprocessors
Store misses cause significant delays in shared-memory multiprocessors because of limited store buffering and ordering constraints required for proper synchronization. Today, prog...
Thomas F. Wenisch, Anastassia Ailamaki, Babak Fals...
ISCA
2007
IEEE
130views Hardware» more  ISCA 2007»
15 years 3 months ago
Dynamic prediction of architectural vulnerability from microarchitectural state
Transient faults due to particle strikes are a key challenge in microprocessor design. Driven by exponentially increasing transistor counts, per-chip faults are a growing burden. ...
Kristen R. Walcott, Greg Humphreys, Sudhanva Gurum...
ISCA
2007
IEEE
171views Hardware» more  ISCA 2007»
15 years 3 months ago
Power provisioning for a warehouse-sized computer
Large-scale Internet services require a computing infrastructure that can be appropriately described as a warehouse-sized computing system. The cost of building datacenter facilit...
Xiaobo Fan, Wolf-Dietrich Weber, Luiz André...
ISCAS
2007
IEEE
92views Hardware» more  ISCAS 2007»
15 years 3 months ago
Macroblock-Level Adaptive Scan Scheme for Discrete Cosine Transform Coefficients
—Discrete Cosine Transform (DCT) has been widely used in image/video coding systems, where zigzag scan is usually employed for DCT coefficient organization. However, due to local...
Li Zhang, Wen Gao, Qiang Wang, Debin Zhao
ISCA
2007
IEEE
152views Hardware» more  ISCA 2007»
15 years 3 months ago
Carbon: architectural support for fine-grained parallelism on chip multiprocessors
Chip multiprocessors (CMPs) are now commonplace, and the number of cores on a CMP is likely to grow steadily. However, in order to harness the additional compute resources of a CM...
Sanjeev Kumar, Christopher J. Hughes, Anthony D. N...