52 search results - page 3 / 11 » isca 2010 |
ISCA
2005
IEEE
15 years 3 months ago
2005
IEEE
Evolving semiconductor and circuit technology has greatly increased the pin bandwidth available to a router chip. In the early 90s, routers were limited to 10Gb/s of pin bandwidth...
DT
2007
14 years 10 months ago
2007
This paper proposes a new heuristic approach to determine the input pattern that minimizes leakage currents of nanometer CMOS circuits during sleep mode considering stack and fano...
DATE
2010
IEEE
15 years 3 months ago
2010
IEEE
When testing delay faults on critical paths, conventional structural test patterns may be applied in functionally-unreachable states, leading to over-testing or under-testing of t...
DATE
2010
IEEE
15 years 15 days ago
2010
IEEE
Various X-filling methods have been proposed for reducing the shift and/or capture power in scan testing. The main drawback of these methods is that X-filling for low power leads t...
DSD
2010
IEEE
14 years 8 months ago
2010
IEEE
— In this paper we propose a new method of test patterns compression based on a design of a dedicated SAT-based ATPG (Automatic Test Pattern Generator). This compression method i...