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ISLPED
1999
ACM
177views Hardware» more  ISLPED 1999»
15 years 1 months ago
Low power synthesis of dual threshold voltage CMOS VLSI circuits
The use of dual threshold voltages can significantly reduce the static power dissipated in CMOS VLSI circuits. With the supply voltage at 1V and threshold voltage as low as 0.2V ...
Vijay Sundararajan, Keshab K. Parhi
ISLPED
1999
ACM
86views Hardware» more  ISLPED 1999»
15 years 1 months ago
Power macro-models for DSP blocks with application to high-level synthesis
Abstract – In this paper, we propose a modeling approach for the average power consumption of macro-blocks that are typically used in digital signal processing (DSP) systems, suc...
Subodh Gupta, Farid N. Najm
ISLPED
1999
ACM
143views Hardware» more  ISLPED 1999»
15 years 1 months ago
Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation
Modern microprocessors employ one or two levels of on-chip cachesto bridge the burgeoning speeddisparities between the processor and the RAM. These SRAM caches are a major source ...
Kanad Ghose, Milind B. Kamble
ISLPED
1999
ACM
47views Hardware» more  ISLPED 1999»
15 years 1 months ago
Databus charge recovery: practical considerations
The charge recovery databus is a scheme which reduces energy consumption through the application of adiabatic circuit techniques. Previous work 2 gives a solid theoretical analysi...
Benjamin Bishop, Mary Jane Irwin
ISLPED
1999
ACM
84views Hardware» more  ISLPED 1999»
15 years 1 months ago
An architectural solution for the inductive noise problem due to clock-gating
As we approach Gigascale Integration, chip power consumption is becoming a critical system parameter. Clock-gating idle units provides needed reductions in power consumption. Howe...
Mondira Deb Pant, Pankaj Pant, D. Scott Wills, Viv...