In this paper we study signal alignment resulting in maximum peak interconnect crosstalk noise. We consider two cases. In the first one we assume that arbitrary arrival times of i...
For a four-layer datapath routing environment, we present an algorithm that considers all the nets simultaneously. Routing probabilities are calculated for potential routing regio...
Suresh Raman, Sachin S. Sapatnekar, Charles J. Alp...
We address the problem of computing critical area for missing material defects in a circuit layout. The extraction of critical area is the main computational problem in VLSI yield...
500+ MHz designs using deep-submicron (DSM) copper interconnects require accurate and efficient modeling of cladding-metals’ frequency-dependent impedance [1]. In this paper, fo...
In this paper, we propose a new clock tree synthesis method for semi-synchronous circuits. A clock tree obtained by the proposed method is a multi-level multi-way clock tree such ...