We propose a procedure for designing an LFSRbased circuit for masking of unknown output values that appear in the output response of a circuit tested using LBIST. The procedure is...
Masao Naruse, Irith Pomeranz, Sudhakar M. Reddy, S...
In a carefully structured study spanning several months, the authors visited numerous companies focused on Design For Test methodologies in SoC Test, Characterization, and Failure...
This paper introduces a finite memory compactor called convolutional compactor that provides compaction ratios of test responses in excess of 100x even for a very small number of ...
Janusz Rajski, Jerzy Tyszer, Chen Wang, Sudhakar M...
At-speed test has become a requirement in IC technologies below 180 nm. Unfortunately, test mode switching activity and IR-drop present special challenges to the successful applic...
Jayashree Saxena, Kenneth M. Butler, Vinay B. Jaya...
Very Deep Sub-Micron (VDSM) defects are resolved as Statistical Post-Processing™ (SPP) outliers of a new IDDQ screen. The screen applies an IDDQ pattern once to the Device Under...
Chris Schuermyer, Brady Benware, Kevin Cota, Rober...