Sciweavers

1057 search results - page 136 / 212
» its 1998
Sort
View
ISSS
1998
IEEE
124views Hardware» more  ISSS 1998»
15 years 2 months ago
Data-Path Synthesis of VLIW Video Signal Processors
This paper describes a methodology for synthesizing the data-path of a Very Long Instruction Word (VLIW) based Video Signal Processor (VSP). Offering both performance and programm...
Zhao Wu, Wayne Wolf
ITC
1998
IEEE
114views Hardware» more  ITC 1998»
15 years 2 months ago
BETSY: synthesizing circuits for a specified BIST environment
This paper presents a logic synthesis tool called BETSY (BIST Environment Testable Synthesis) for synthesizing circuits that achieve complete (100%)fault coverage in a user specif...
Zhe Zhao, Bahram Pouya, Nur A. Touba
MICRO
1998
IEEE
129views Hardware» more  MICRO 1998»
15 years 2 months ago
A Bandwidth-efficient Architecture for Media Processing
Media applications are characterized by large amounts of available parallelism, little data reuse, and a high computation to memory access ratio. While these characteristics are p...
Scott Rixner, William J. Dally, Ujval J. Kapasi, B...
NDSS
1998
IEEE
15 years 2 months ago
Enabling the Internet White Pages Service - the Directory Guardian
The Internet White Pages Service (IWPS) has been slow to materialise for many reasons. One of them is the security concerns that organisations have, over allowing the public to ga...
David W. Chadwick, Andrew J. Young
RTSS
1998
IEEE
15 years 2 months ago
Statistical Delay Guarantee of Virtual Clock
In this paper, we derive a statistical delay guarantee of the generalized Virtual Clock scheduling algorithm. We define the concept of an equivalent fluid and packet source and pr...
Pawan Goyal, Harrick M. Vin