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MICRO
1999
IEEE
115views Hardware» more  MICRO 1999»
15 years 1 months ago
Fetch Directed Instruction Prefetching
Instruction supply is a crucial component of processor performance. Instruction prefetching has been proposed as a mechanism to help reduce instruction cache misses, which in turn...
Glenn Reinman, Brad Calder, Todd M. Austin
MICRO
1999
IEEE
102views Hardware» more  MICRO 1999»
15 years 1 months ago
Evaluation of a High Performance Code Compression Method
Compressing the instructions of an embedded program is important for cost-sensitive low-power control-oriented embedded computing. A number of compression schemes have been propos...
Charles Lefurgy, Eva Piccininni, Trevor N. Mudge
MICRO
1999
IEEE
131views Hardware» more  MICRO 1999»
15 years 1 months ago
Value Prediction for Speculative Multithreaded Architectures
The speculative multithreading paradigm (speculative threadlevel parallelism) is based on the concurrent execution of control-speculative threads. The efficiency of microarchitect...
Pedro Marcuello, Jordi Tubella, Antonio Gonz&aacut...
MICRO
1999
IEEE
110views Hardware» more  MICRO 1999»
15 years 1 months ago
Balance Scheduling: Weighting Branch Tradeoffs in Superblocks
Since there is generally insufficient instruction level parallelism within a single basic block, higher performance is achieved by speculatively scheduling operations in superbloc...
Alexandre E. Eichenberger, Waleed Meleis
110
Voted
MICRO
1999
IEEE
143views Hardware» more  MICRO 1999»
15 years 1 months ago
Code Transformations to Improve Memory Parallelism
Current microprocessors incorporate techniques to exploit instruction-level parallelism (ILP). However, previous work has shown that these ILP techniques are less effective in rem...
Vijay S. Pai, Sarita V. Adve