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MICRO
2000
IEEE
107views Hardware» more  MICRO 2000»
15 years 1 months ago
Register integration: a simple and efficient implementation of squash reuse
Register integration (or simply integration) is a mechanism for incorporating speculative results directly into a sequential execution using data-dependence relationships. In this...
Amir Roth, Gurindar S. Sohi
MICRO
2000
IEEE
124views Hardware» more  MICRO 2000»
15 years 2 months ago
Calpa: a tool for automating selective dynamic compilation
Selective dynamic compilation systems, typically driven by annotations that identify run-time constants, can achieve significant program speedups. However, manually inserting ann...
Markus Mock, Craig Chambers, Susan J. Eggers
MICRO
2000
IEEE
98views Hardware» more  MICRO 2000»
15 years 2 months ago
The store-load address table and speculative register promotion
Register promotion is an optimization that allocates a value to a register for a region of its lifetime where it is provably not aliased. Conventional compiler analysis cannot alw...
Matt Postiff, David Greene, Trevor N. Mudge
MICRO
2000
IEEE
86views Hardware» more  MICRO 2000»
15 years 2 months ago
On pipelining dynamic instruction scheduling logic
A machine’s performance is the product of its IPC (Instructions Per Cycle) and clock frequency. Recently, Palacharla, Jouppi, and Smith [3] warned that the dynamic instruction s...
Jared Stark, Mary D. Brown, Yale N. Patt
MICRO
2000
IEEE
96views Hardware» more  MICRO 2000»
15 years 2 months ago
Instruction distribution heuristics for quad-cluster, dynamically-scheduled, superscalar processors
We investigate instruction distribution methods for quadcluster, dynamically-scheduled superscalar processors. We study a variety of methods with different cost, performance and c...
Amirali Baniasadi, Andreas Moshovos