101 search results - page 15 / 21 » micro 2000 |
MICRO
2002
IEEE
15 years 2 months ago
2002
IEEE
In this paper we present an approach to boosting performance and tolerating latency by deferring non-critical instructions into a deferred queue for later processing. As such, ins...
MICRO
2003
IEEE
15 years 2 months ago
2003
IEEE
Single-event upsets from particle strikes have become a key challenge in microprocessor design. Techniques to deal with these transient faults exist, but come at a cost. Designers...
MICRO
2008
IEEE
15 years 4 months ago
2008
IEEE
It is well recognized that LRU cache-line replacement can be ineffective for applications with large working sets or non-localized memory access patterns. Specifically, in lastle...
MICRO
2006
IEEE
15 years 3 months ago
2006
IEEE
The superblock is a scheduling region which exposes instruction level parallelism beyond the basic block through speculative execution of instructions. In general, scheduling supe...
MICRO
2003
IEEE
15 years 2 months ago
2003
IEEE
With power dissipation becoming an increasingly vexing problem across many classes of computer systems, measuring power dissipation of real, running systems has become crucial for...