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MICRO
2010
IEEE
154views Hardware» more  MICRO 2010»
14 years 7 months ago
Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory
High density memory is becoming more important as many execution streams are consolidated onto single chip many-core processors. DRAM is ubiquitous as a main memory technology, but...
Jeffrey Stuecheli, Dimitris Kaseridis, Hillery C. ...
ACSD
2010
IEEE
215views Hardware» more  ACSD 2010»
14 years 7 months ago
A Formal Semantics of Clock Refinement in Imperative Synchronous Languages
The synchronous model of computation divides the execution of a program into an infinite sequence of socalled macro steps, which are further divided into finitely many micro steps....
Mike Gemunde, Jens Brandt, Klaus Schneider
HAPTICS
2010
IEEE
14 years 11 months ago
Haptic Feedback of Piconewton Interactions with Optical Tweezers
Haptic feedback for micro- and nanomanipulation is a research area of growing importance with many potential applications in micro- and biotechnology. Past research often involves ...
Cécile Pacoret, Arvid Bergander, Stephane R...
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MICRO
2010
IEEE
115views Hardware» more  MICRO 2010»
14 years 8 months ago
Per-Thread Cycle Accounting
This paper proposes a cycle accounting architecture for Simultaneous Multithreading (SMT) processors that estimates the execution times for each of the threads had they been execu...
Stijn Eyerman, Lieven Eeckhout
MICRO
2010
IEEE
149views Hardware» more  MICRO 2010»
14 years 7 months ago
ReMAP: A Reconfigurable Heterogeneous Multicore Architecture
This paper presents ReMAP, a reconfigurable architecture geared towards accelerating and parallelizing applications within a heterogeneous CMP. In ReMAP, threads share a common rec...
Matthew A. Watkins, David H. Albonesi