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VLSID
2006
IEEE
170views VLSI» more  VLSID 2006»
15 years 10 months ago
On the Implementation of a Low-Power IEEE 802.11a Compliant Viterbi Decoder
This article describes a standard cell based novel implementation of a low-power Viterbi Decoder (VD) targeted for the IEEE 802.11a Wireless LAN system. Multiple clock rates have ...
Koushik Maharatna, Alfonso Troya, Milos Krstic, Ec...
VLSID
2006
IEEE
170views VLSI» more  VLSID 2006»
15 years 10 months ago
16-Bit Segmented Type Current Steering DAC for Video Applications
In this paper, 16-bit, 50 MHz Current Steering DAC is designed. This DAC is implemented using TSMC 0.35 ?m technology. An optimum segmentation is done of 16-bits into binary and t...
Gaurav Raja, Basabi Bhaumik
IJCNN
2006
IEEE
15 years 4 months ago
Implementing Synaptic Plasticity in a VLSI Spiking Neural Network Model
— This paper describes an area-efficient mixed-signal implementation of synapse-based long term plasticity realized in a VLSI1 model of a spiking neural network. The artificial...
Johannes Schemmel, Andreas Grübl, Karlheinz M...
ISCAS
2006
IEEE
103views Hardware» more  ISCAS 2006»
15 years 4 months ago
A low-power geometric mapping co-processor for high-speed graphics application
Abstract— In this article we present a novel design of a lowpower geometric mapping co-processor that can be used for high-performance graphics system. The processor can carry ou...
S. Leeke, L. Maharatna
LCN
2006
IEEE
15 years 4 months ago
Experimental and Analytical Evaluation of Available Bandwidth Estimation Tools
In this paper, we present a low cost and flexible testbed to evaluate the performance of available bandwidth estimation tools in a common and controlled environment. In addition,...
Cesar D. Guerrero, Miguel A. Labrador