This article describes a standard cell based novel implementation of a low-power Viterbi Decoder (VD) targeted for the IEEE 802.11a Wireless LAN system. Multiple clock rates have ...
Koushik Maharatna, Alfonso Troya, Milos Krstic, Ec...
In this paper, 16-bit, 50 MHz Current Steering DAC is designed. This DAC is implemented using TSMC 0.35 ?m technology. An optimum segmentation is done of 16-bits into binary and t...
— This paper describes an area-efficient mixed-signal implementation of synapse-based long term plasticity realized in a VLSI1 model of a spiking neural network. The artificial...
Abstract— In this article we present a novel design of a lowpower geometric mapping co-processor that can be used for high-performance graphics system. The processor can carry ou...
In this paper, we present a low cost and flexible testbed to evaluate the performance of available bandwidth estimation tools in a common and controlled environment. In addition,...