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DATE
2002
IEEE
131views Hardware» more  DATE 2002»
15 years 10 months ago
Passive Constrained Rational Approximation Algorithm Using Nevanlinna-Pick Interpolation
As system integration evolves and tighter design constraints must be met, it becomes necessary to account for the non-ideal behavior of all the elements in a system. For high-spee...
Carlos P. Coelho, Luis Miguel Silveira, Joel R. Ph...
DATE
2002
IEEE
94views Hardware» more  DATE 2002»
15 years 10 months ago
FACTOR: A Hierarchical Methodology for Functional Test Generation and Testability Analysis
This paper develops an improved approach for hierarchical functional test generation for complex chips. In order to deal with the increasing complexity of functional test generati...
Vivekananda M. Vedula, Jacob A. Abraham
DSD
2002
IEEE
90views Hardware» more  DSD 2002»
15 years 10 months ago
Simplifying Instruction Issue Logic in Superscalar Processors
Modern microprocessors schedule instructions dynamically in order to exploit instruction-level parallelism. It is necessary to increase instruction window size for improving instr...
Toshinori Sato, Itsujiro Arita
DSN
2002
IEEE
15 years 10 months ago
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to...
Premkishore Shivakumar, Michael Kistler, Stephen W...
DSN
2002
IEEE
15 years 10 months ago
Performability Analysis of Guarded-Operation Duration: A Successive Model-Translation Approach
When making an engineering design decision, it is often necessary to consider its implications on both system performance and dependability. In this paper, we present a performabi...
Ann T. Tai, William H. Sanders, Leon Alkalai, Savi...