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PPL
2008
96views more  PPL 2008»
15 years 11 days ago
A Hybrid Shared Memory Execution Model for a Data Parallel Language with I/O
Execution of programs with data parallel language constructs is either based on the fork/join or on the SPMD model. Whereas the former executes a program sequentially and confines...
Clemens Grelck, Steffen Kuthe, Sven-Bodo Scholz
PPL
2008
144views more  PPL 2008»
15 years 11 days ago
Rapid Prototyping of the Data-Driven Chip-Multiprocessor (d2-CMP) Using FPGAs
This paper presents the FPGA implementation of the prototype for the Data-Driven Chip-Multiprocessor (D2-CMP). In particular, we study the implementation of a Thread Synchronizati...
Konstantinos Tatas, Costas Kyriacou, Paraskevas Ev...
98
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PPL
2008
264views more  PPL 2008»
15 years 11 days ago
A Performance Evaluation of the Nehalem Quad-Core Processor for Scientific Computing
In this work we present an initial performance evaluation of Intel's latest, secondgeneration quad-core processor, Nehalem, and provide a comparison to first-generation AMD a...
Kevin J. Barker, Kei Davis, Adolfy Hoisie, Darren ...
96
Voted
BMCBI
2008
111views more  BMCBI 2008»
15 years 17 days ago
MLIP: using multiple processors to compute the posterior probability of linkage
Background: Localization of complex traits by genetic linkage analysis may involve exploration of a vast multidimensional parameter space. The posterior probability of linkage (PP...
Manika Govil, Alberto Maria Segre, Veronica J. Vie...
PPL
2008
185views more  PPL 2008»
15 years 11 days ago
On Design and Application Mapping of a Network-on-Chip(NoC) Architecture
As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either ...
Jun Ho Bahn, Seung Eun Lee, Yoon Seok Yang, Jungso...