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76
Voted
HPCA
2006
IEEE
15 years 11 months ago
2006
IEEE
We propose dynamic scheduler designs to improve the scheduler scalability and reduce its complexity in the SMT processors. Our first design is an adaptation of the recently propos...
93
Voted
HPCA
2006
IEEE
15 years 11 months ago
2006
IEEE
In high-end processors, increasing the number of in-flight instructions can improve performance by overlapping useful processing with long-latency accesses to the main memory. Buf...
MICRO
2006
IEEE
15 years 5 months ago
2006
IEEE
One of the main challenges of modern processor design is the implementation of a scalable and efficient mechanism to detect memory access order violations as a result of out-of-o...
110
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ISCC
2006
IEEE
15 years 5 months ago
2006
IEEE
Network resource management and control is a complex problem that requires robust, possibly intelligent, control methodologies to obtain satisfactory performance. While many Activ...
GLOBECOM
2006
IEEE
15 years 5 months ago
2006
IEEE
In this paper, the performance model for a lossless OBS edge node is built with respect to the queueing performance of the transmission buffer. In contrast to the shaping effect...