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ISCAS
2005
IEEE
147views Hardware» more  ISCAS 2005»
15 years 5 months ago
A heuristic approach for multiple restricted multiplication
— This paper introduces a heuristic solution to the multiple restricted multiplication (MRM) optimization problem. MRM refers to a situation where a single variable is multiplied...
Nalin Sidahao, George A. Constantinides, Peter Y. ...
ISCAS
2005
IEEE
115views Hardware» more  ISCAS 2005»
15 years 5 months ago
A framework for the design of error-aware power-efficient fixed-width Booth multipliers
In this paper, a framework of designing a low-error and power-efficient two’s-complement fixed-width Booth multiplier that receives two n-bit numbers and produces an n-bit produ...
Min-An Song, Lan-Da Van, Chih-Chyau Yang, Shih-Chi...
ISCAS
2005
IEEE
190views Hardware» more  ISCAS 2005»
15 years 5 months ago
Digital VLSI OFDM transceiver architecture for wireless SoC design
—This paper presents the VLSI architecture of an OFDM baseband transceiver for wireless communications. The open-/closed-loop carrier recovery achieves the stepping frequency acq...
Wei-Hsiang Tseng, Ching-Chi Chang, Chorng-Kuang Wa...
ISIPTA
2005
IEEE
125views Mathematics» more  ISIPTA 2005»
15 years 5 months ago
Evidential modeling for pose estimation
Pose estimation involves reconstructing the configuration of a moving body from images sequences. In this paper we present a general framework for pose estimation of unknown obje...
Fabio Cuzzolin, Ruggero Frezza
ISMVL
2005
IEEE
86views Hardware» more  ISMVL 2005»
15 years 5 months ago
Multiple-Valued Duplex Asynchronous Data Transfer Scheme for Interleaving in LDPC Decoders
A novel duplex asynchronous data-transfer scheme based on multiple-valued encoding is proposed for interleaving in Low-Density Parity-Check (LDPC) decoders, where high-throughput ...
Naoya Onizawa, Akira Mochizuki, Takahiro Hanyu