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DATE
2008
IEEE
116views Hardware» more  DATE 2008»
15 years 4 months ago
A Variation Aware High Level Synthesis Framework
— The worst-case delay/power of function units has been used in traditional high level synthesis to facilitate design space exploration. As technology scales to nanometer regime,...
Feng Wang 0004, Guangyu Sun, Yuan Xie
DATE
2008
IEEE
143views Hardware» more  DATE 2008»
15 years 4 months ago
Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming
Multi-input addition is an important operation for many DSP and video processing applications. On FPGAs, multi-input addition has traditionally been implemented using trees of car...
Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
DATE
2008
IEEE
131views Hardware» more  DATE 2008»
15 years 4 months ago
Scheduling of Fault-Tolerant Embedded Systems with Soft and Hard Timing Constraints
In this paper we present an approach to the synthesis of fault-tolerant schedules for embedded applications with soft and hard real-time constraints. We are interested to guarante...
Viacheslav Izosimov, Paul Pop, Petru Eles, Zebo Pe...
DATE
2008
IEEE
121views Hardware» more  DATE 2008»
15 years 4 months ago
A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy
We define a robust fault model as a model where the existence of an undetectable fault implies the existence of logic redundancy, or more generally, a suboptimality in the synthe...
Irith Pomeranz, Sudhakar M. Reddy
FGR
2008
IEEE
322views Biometrics» more  FGR 2008»
15 years 4 months ago
Statistical appearance models for automatic pose invariant face recognition
Recent pose invariant methods try to model the subject specific appearance change across pose. For this, however, almost all of the existing methods require a perfect alignment b...
M. Saquib Sarfraz, Olaf Hellwich