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TCAD
1998
82views more  TCAD 1998»
13 years 5 months ago
LOT: Logic Optimization with Testability. New transformations for logic synthesis
—A new approach to optimize multilevel logic circuits is introduced. Given a multilevel circuit, the synthesis method optimizes its area while simultaneously enhancing its random...
Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang K...
TCAD
1998
126views more  TCAD 1998»
13 years 5 months ago
Iterative remapping for logic circuits
Abstract—This paper presents an aggressive optimization technique targeting combinational logic circuits. Starting from an initial implementation mapped on a given technology lib...
Luca Benini, Patrick Vuillod, Giovanni De Micheli
TCAD
1998
96views more  TCAD 1998»
13 years 5 months ago
Diagnosis of clustered faults and wafer testing
—A probabilistic diagnosis algorithm is presented for constant degree structures. The performance of the algorithm is analyzed under a negative binomial failure distribution to a...
Kaiyuan Huang, Vinod K. Agarwal, Krishnaiyan Thula...
TCAD
1998
107views more  TCAD 1998»
13 years 5 months ago
Optimizing dominant time constant in RC circuits
— Conventional methods for optimal sizing of wires and transistors use linear resistor-capacitor (RC) circuit models and the Elmore delay as a measure of signal delay. If the RC ...
Lieven Vandenberghe, Stephen P. Boyd, Abbas A. El ...
TCAD
1998
127views more  TCAD 1998»
13 years 5 months ago
Gate-level power estimation using tagged probabilistic simulation
In this paper, we present a probabilistic simulation technique to estimate the power consumption of a cmos circuit under a general delay model. This technique is based on the noti...
Chih-Shun Ding, Chi-Ying Tsui, Massoud Pedram