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ICCAD
1994
IEEE
95views Hardware» more  ICCAD 1994»
15 years 4 months ago
Provably correct high-level timing analysis without path sensitization
- This paper addresses the problem of true delay estimation during high level design. The existing delay estimation techniques either estimate the topological delay of the circuit ...
Subhrajit Bhattacharya, Sujit Dey, Franc Brglez
100
Voted
DAC
1994
ACM
15 years 4 months ago
Performance-Driven Simultaneous Place and Route for Row-Based FPGAs
Sequential place and route tools for FPGAs are inherently weak at addressing both wirability and timing optimizations. This is primarily due to the difficulty in predicting these ...
Sudip Nag, Rob A. Rutenbar
FOCS
1994
IEEE
15 years 4 months ago
Expander Codes
Sipser and Spielman have introduced a constructive family of asymptotically good linear error-correcting codes--expander codes--together with a simple parallel algorithm that will ...
Michael Sipser, Daniel A. Spielman
INFOCOM
1994
IEEE
15 years 4 months ago
Dynamic Bandwidth Allocation for Efficient Transport of Real-Time VBR Video over ATM
This pape? presents a novel approach to dynamic transmission bandwidth allocation for transport of real-time variable-bit-rate video in ATM networks. Describe video traffic in the...
Song Chong, San-qi Li, Joydeep Ghosh
118
Voted
ICALP
1994
Springer
15 years 4 months ago
Liveness in Timed and Untimed Systems
When provingthe correctness of algorithmsin distributed systems, one generally considers safety conditions and liveness conditions. The Input Output I O automaton model and its ti...
Rainer Gawlick, Roberto Segala, Jørgen F. S...