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VLSID
1999
IEEE
97views VLSI» more  VLSID 1999»
15 years 5 months ago
A New Methodology for Concurrent Technology Development and Cell Library Optimization
To minimize the time to market and cost of new sub 0.25um process technologies and products, PDF Solutions, Inc., has developed a new comprehensive approach based on the use of pr...
Marko P. Chew, Sharad Saxena, Thomas F. Cobourn, P...
83
Voted
VLSID
1999
IEEE
64views VLSI» more  VLSID 1999»
15 years 5 months ago
Exact Output Response Computation of RC Interconnects under Polynomial Input Waveforms
Accurate output response computation of RC interconnects under various input excitations is a key issue in deep submicron delay analysis.In this paper,we present an exact analysis...
Satrajit Gupta, Lalit M. Patnaik
VLSID
1999
IEEE
100views VLSI» more  VLSID 1999»
15 years 5 months ago
Improved Effective Capacitance Computations for Use in Logic and Layout Optimization
We describe an improved iterationless approach for computing the effective capacitance of an interconnect load at a driving gate output. The speed and accuracy of our approach mak...
Andrew B. Kahng, Sudhakar Muddu
VTS
1999
IEEE
108views Hardware» more  VTS 1999»
15 years 5 months ago
Adaptive Techniques for Improving Delay Fault Diagnosis
This paper presents adaptive techniques for improving delay fault diagnosis. These techniques reduce the search space for direct probing which can save a lot of time during failur...
Jayabrata Ghosh-Dastidar, Nur A. Touba
113
Voted
VTS
1999
IEEE
125views Hardware» more  VTS 1999»
15 years 5 months ago
Error Detecting Refreshment for Embedded DRAMs
This paper presents a new technique for on-line consistency checking of embedded DRAMs. The basic idea is to use the periodic refresh operation for concurrently computing a test c...
Sybille Hellebrand, Hans-Joachim Wunderlich, Alexa...