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ARITH
1999
IEEE
15 years 10 months ago
Reduced Latency IEEE Floating-Point Standard Adder Architectures
The design and implementation of a double precision floating-point IEEE-754 standard adder is described which uses "flagged prefix addition" to merge rounding with the s...
Andrew Beaumont-Smith, Neil Burgess, S. Lefrere, C...
ARITH
1999
IEEE
15 years 10 months ago
High-Speed Inverse Square Roots
Inverse square roots are used in several digital signal processing, multimedia, and scientific computing applications. This paper presents a high-speed method for computing invers...
Michael J. Schulte, Kent E. Wires
CA
1999
IEEE
15 years 10 months ago
Fast Synthetic Vision, Memory, and Learning Models for Virtual Humans
This paper presents a simple and efficient method of modeling synthetic vision, memory, and learning for autonomous animated characters in real-time virtual environments. The mode...
James J. Kuffner Jr., Jean-Claude Latombe
CGI
1999
IEEE
15 years 10 months ago
Volume Decimation of Irregular Tetrahedral Grids
Rendering highly complex models can be time and space prohibitive, and decimation is an important tool in providing simplifications. A decimated model may replace the original ent...
Allen Van Gelder, Vivek Verma, Jane Wilhelms
CODES
1999
IEEE
15 years 10 months ago
System synthesis utilizing a layered functional model
We propose a system synthesis method which bridges the gap between a highly abstract functional model and an efficient hardware or software implementation. The functional model is...
Ingo Sander, Axel Jantsch