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ASAP
2000
IEEE
184views Hardware» more  ASAP 2000»
15 years 9 months ago
Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter
Sorting long sequences of keys is a problem that occurs in many different applications. For embedded systems, a uniprocessor software solution is often not applicable due to the l...
Marcus Bednara, Oliver Beyer, Jürgen Teich, R...
DATE
2000
IEEE
103views Hardware» more  DATE 2000»
15 years 9 months ago
Protocol Stack-Based Telecom-Emulator
The paper describes the concept and implementation of a telecom emulator that features both recon gurability and high-speed processing. The emulator can be easily transmuted into ...
Takahiro Murooka, Toshiaki Miyazaki
IJCNN
2000
IEEE
15 years 9 months ago
Hardware Implementation of a PCA Learning Network by an Asynchronous PDM Digital Circuit
We have fabricated a PCA (Principal Component Analysis) learning network in a FPGA (Field Programmable Gate Array) by using an asynchronous PDM (Pulse Density Modulation) digital ...
Yuzo Hirai, Kuninori Nishizawa
ISMVL
2000
IEEE
120views Hardware» more  ISMVL 2000»
15 years 9 months ago
Mod-p Decision Diagrams: A Data Structure for Multiple-Valued Functions
Multiple-valued decision diagrams (MDDs) give a way of approaching problems by using symbolic variables which are often more naturally associated with the problem statement than t...
Harald Sack, Elena Dubrova, Christoph Meinel
GECCO
2000
Springer
104views Optimization» more  GECCO 2000»
15 years 8 months ago
Quadratic Bloat in Genetic Programming
In earlier work we predicted program size would grow in the limit at a quadratic rate and up to fty generations we measured bloat O(generations1:2;1:5). On two simple benchmarks w...
William B. Langdon