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2000
IEEE
87views Hardware» more  DATE 2000»
15 years 10 months ago
Multi-Node Static Logic Implications for Redundancy Identification
This paper presents a method for redundancy identification (RID) using multi-node logic implications. The algorithm discovers a large number of direct and indirect implications b...
Kabir Gulrajani, Michael S. Hsiao
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DATE
2000
IEEE
90views Hardware» more  DATE 2000»
15 years 10 months ago
Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip Design
We present a technique for fast estimation of the power consumed by the cache and bus sub-system of a parameterized system-on-a-chip design for a given application. The technique ...
Jörg Henkel, Tony Givargis, Frank Vahid
DATE
2000
IEEE
128views Hardware» more  DATE 2000»
15 years 10 months ago
A Bus Delay Reduction Technique Considering Crosstalk
As the CMOS technology scaled down, the horizontal coupling capacitance between adjacent wires plays dominant part in wire load, crosstalk interference becomes a serious problem f...
Kei Hirose, Hiroto Yasuura
DATE
2000
IEEE
121views Hardware» more  DATE 2000»
15 years 10 months ago
Composite Signal Flow: A Computational Model Combining Events, Sampled Streams, and Vectors
The composite signal flow model of computation targets systems with significant control and data processing parts. It builds on the data flow and synchronous data flow models ...
Axel Jantsch, Per Bjuréus
DATE
2000
IEEE
83views Hardware» more  DATE 2000»
15 years 10 months ago
Predicting Coupled Noise in RC Circuits
A novel method which can be regarded as the noisecounterpart of the celebrated Elmore’s delay formula— both being based on the first two moments of the network’s transfer fu...
Bernard N. Sheehan