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ISCA
2000
IEEE
105views Hardware» more  ISCA 2000»
15 years 10 months ago
Multiple-banked register file architectures
The register file access time is one of the critical delays in current superscalar processors. Its impact on processor performance is likely to increase in future processor genera...
José-Lorenzo Cruz, Antonio González,...
168
Voted
WOSP
2000
ACM
15 years 10 months ago
Expressing meaningful processing requirements among heterogeneous nodes in an active network
Active Network technology envisions deployment of virtual execution environments within network elements, such as switches and routers. As a result, nonhomogeneous processing can ...
Virginie Galtier, Kevin L. Mills, Yannick Carlinet...
SWAT
2000
Springer
90views Algorithms» more  SWAT 2000»
15 years 9 months ago
Efficient Expected-Case Algorithms for Planar Point Location
Planar point location is among the most fundamental search problems in computational geometry. Although this problem has been heavily studied from the perspective of worst-case que...
Sunil Arya, Siu-Wing Cheng, David M. Mount, Ramesh...
186
Voted
SIAMCOMP
2000
118views more  SIAMCOMP 2000»
15 years 6 months ago
Constructive, Deterministic Implementation of Shared Memory on Meshes
This paper describes a scheme to implement a shared address space of size m on an n-node mesh, with m polynomial in n, where each mesh node hosts a processor and a memory module. A...
Andrea Pietracaprina, Geppino Pucci, Jop F. Sibeyn
177
Voted
RTSS
2000
IEEE
15 years 9 months ago
Efficient Scheduling of Sporadic, Aperiodic, and Periodic Tasks with Complex Constraints
Many industrial applications with real-time demands are composed of mixed sets of tasks with a variety of requirements. These can be in the form of standard timing constraints, su...
Damir Isovic, Gerhard Fohler