Sciweavers

2056 search results - page 280 / 412
» time 2000
Sort
View
HPCA
2001
IEEE
16 years 6 months ago
Reducing DRAM Latencies with an Integrated Memory Hierarchy Design
In this papel; we address the severe performance gap caused by high processor clock rates and slow DRAM accesses. We show that even with an aggressive, next-generation memory syst...
Wei-Fen Lin, Steven K. Reinhardt, Doug Burger
ICCD
2008
IEEE
370views Hardware» more  ICCD 2008»
16 years 3 months ago
Simulation points for SPEC CPU 2006
— Increasing sizes of benchmarks make detailed simulation an extremely time consuming process. Statistical techniques such as the SimPoint methodology have been proposed in order...
Arun A. Nair, Lizy K. John
ICCAD
2002
IEEE
143views Hardware» more  ICCAD 2002»
16 years 2 months ago
A Markov chain sequence generator for power macromodeling
In macromodeling-based power estimation, circuit macromodels are created from simulations of synthetic input vector sequences. Fast generation of these sequences with all possible...
Xun Liu, Marios C. Papaefthymiou
153
Voted
ICCAD
2001
IEEE
163views Hardware» more  ICCAD 2001»
16 years 2 months ago
Predicting the Performance of Synchronous Discrete Event Simulation Systems
In this paper we propose a model to predict the performance of synchronous discrete event simulation. The model considers parameters including the number of active objects per cyc...
Jinsheng Xu, Moon-Jung Chung
ICST
2009
IEEE
16 years 21 days ago
Seasonal Variation in the Vulnerability Discovery Process
Vulnerability discovery rates need to be taken into account for evaluating security risks. Accurate projection of these rates is required to estimate the effort needed to develop ...
HyunChul Joh, Yashwant K. Malaiya