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IPPS
2006
IEEE
16 years 2 days ago
Dynamically reconfigurable cache architecture using adaptive block allocation policy
In this paper, we present a dynamically reconfigurable cache architecture using adaptive block allocation policy analyzed by means of simulation. Our main objectives are: to propo...
Milene Barbosa Carvalho, Luís Fabríc...
APCSAC
2005
IEEE
15 years 11 months ago
Comparing Low-Level Behavior of SPEC CPU and Java Workloads
Java workloads are becoming more prominent on a wide range of computing devices. In contrast to so-called traditional workloads written in C and Fortran, Java workloads are object-...
Andy Georges, Lieven Eeckhout, Koen De Bosschere
184
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IEEEPACT
2005
IEEE
15 years 11 months ago
Design and Implementation of a Compiler Framework for Helper Threading on Multi-core Processors
Helper threading is a technique that utilizes a second core or logical processor in a multi-threaded system to improve the performance of the main thread. A helper thread executes...
Yonghong Song, Spiros Kalogeropulos, Partha Tiruma...
HIPEAC
2005
Springer
15 years 11 months ago
Dynamic Code Region (DCR) Based Program Phase Tracking and Prediction for Dynamic Optimizations
Detecting and predicting a program’s execution phases are crucial to dynamic optimizations and dynamically adaptable systems. This paper shows that a phase can be associated with...
Jinpyo Kim, Sreekumar V. Kodakara, Wei-Chung Hsu, ...
WMPI
2004
ACM
15 years 11 months ago
Understanding the effects of wrong-path memory references on processor performance
High-performance out-of-order processors spend a significant portion of their execution time on the incorrect program path even though they employ aggressive branch prediction al...
Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale ...