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DATE
2002
IEEE
95views Hardware» more  DATE 2002»
15 years 9 months ago
Optimal Transistor Tapering for High-Speed CMOS Circuits
Transistor tapering is a widely used technique applied to optimize the geometries of CMOS transistors in highperformance circuit design with a view to minimizing the delay of a FE...
Li Ding 0002, Pinaki Mazumder
DATE
2002
IEEE
98views Hardware» more  DATE 2002»
15 years 9 months ago
A New ATPG Algorithm to Limit Test Set Size and Achieve Multiple Detections of All Faults
Deterministic observation and random excitation of fault sites during the ATPG process dramatically reduces the overall defective part level. However, multiple observations of eac...
Sooryong Lee, Brad Cobb, Jennifer Dworak, Michael ...
DATE
2002
IEEE
128views Hardware» more  DATE 2002»
15 years 9 months ago
Arbitrary Convex and Concave Rectilinear Module Packing Using TCG
In this paper, we deal with arbitrary convex and concave rectilinear module packing using the Transitive Closure Graph (TCG) representation. The geometric meanings of modules are ...
Jai-Ming Lin, Hsin-Lung Chen, Yao-Wen Chang
DELTA
2002
IEEE
15 years 9 months ago
Teaching Integrated Circuit and Semiconductor Device Design in New Zealand: The University of Canterbury Approach
Teaching the practical aspects of device and chip design in New Zealand presents many problems, including high manufacturing costs, long lead times, and the lack of local industry...
Richard J. Blaikie, Maan M. Alkaisi, Steven M. Dur...
DEXAW
2002
IEEE
145views Database» more  DEXAW 2002»
15 years 9 months ago
An Architecture for Collaboratively Assembled Moderated Information Bearing Web Sites
As originally conceived, the World Wide Web was intended for the purpose of sharing information. Many websites realise this aim by publishing pages from a data repository which su...
Richard Cooper