Abstract. We establish mutual translations between the classes of 1safe timed-arc Petri nets (and its extension with testing arcs) and networks of timed automata (and its subclass ...
This paper presents a two-step, RC-interconnect insensitive linear time-varying (LTV) driver model for gate-level timing calculation. We show how to characterize a driver with the...
As computer systems become increasingly internetworked, there is a growing class of distributed realtime embedded (DRE) applications that have characteristics and present challeng...
Joseph P. Loyall, Richard E. Schantz, David Corman...
Recent study shows that the existing first order canonical timing model is not sufficient to represent the dependency of the gate delay on the variation sources when processing an...
Lizheng Zhang, Weijen Chen, Yuhen Hu, John A. Gubn...