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172
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DATE
2005
IEEE
154views Hardware» more  DATE 2005»
15 years 11 months ago
A Time Slice Based Scheduler Model for System Level Design
Efficient evaluation of design choices, in terms of selection of algorithms to be implemented as hardware or software, and finding an optimal hw/sw design mix is an important re...
Luciano Lavagno, Claudio Passerone, Vishal Shah, Y...
DATE
2005
IEEE
107views Hardware» more  DATE 2005»
15 years 11 months ago
On Statistical Timing Analysis with Inter- and Intra-Die Variations
In this paper, we highlight a fast, effective and practical statistical approach that deals with inter and intra-die variations in VLSI chips. Our methodology is applied to a numb...
Hratch Mangassarian, Mohab Anis
155
Voted
DSN
2005
IEEE
15 years 11 months ago
A Framework for Node-Level Fault Tolerance in Distributed Real-Time Systems
This paper describes a framework for achieving node-level fault tolerance (NLFT) in distributed realtime systems. The objective of NLFT is to mask errors at the node level in orde...
Joakim Aidemark, Peter Folkesson, Johan Karlsson
161
Voted
ECRTS
2005
IEEE
15 years 11 months ago
Energy Aware Non-Preemptive Scheduling for Hard Real-Time Systems
Slowdown based on dynamic voltage scaling (DVS) provides the ability to perform an energy-delay tradeoff in the system. Non-preemptive scheduling becomes an integral part of syste...
Ravindra Jejurikar, Rajesh K. Gupta
ECRTS
2005
IEEE
15 years 11 months ago
A Space-Optimal Wait-Free Real-Time Synchronization Protocol
We present a wait-free protocol for the single-writer, multiple-reader problem in small-memory, embedded real-time systems. We analytically establish that our protocol requires le...
Hyeonjoong Cho, Binoy Ravindran, E. Douglas Jensen