Reader preference, writer preference, and task-fair readerwriter locks are shown to cause undue blocking in multiprocessor real-time systems. A new phase-fair reader-writer lock i...
Nuno Tom?s Daniel Gon?alves With the growing volume of digital information users must deal with, management and retrieval tasks have become increasingly problematic. A popular way ...
- The FPGA (re)configuration is a time-consuming process and a bottleneck in FPGA-based Run-Time Reconfigurable (RTR) systems. In this paper, we present a High Level Synthesis (HLS...
Mahmood Fazlali, Ali Zakerolhosseini, Mojtaba Sabe...
— In this paper we describe a method for bridging internet time delays in a teleoperation scenario. In the scenario, the sizes of the time delays is not only stochastic, but it i...
In this paper, we focus on the synthesis of secure timed systems which are given by timed automata. The security property that the system must satisfy is a non-interference propert...