— We present a new multi-rate architecture for decoding irregular LDPC codes in IEEE 802.16e WiMax standard. The proposed architecture utilizes the value–reuse property of offs...
Kiran K. Gunnam, Gwan S. Choi, Mark B. Yeary, Moha...
Abstract— A programmable analog array inspired from neuronal spike event coding is presented. A configurable event block forms the basic building block of the programmable array...
Thomas Jacob Koickal, Alister Hamilton, Luiz C. P....
DSM and nanometer VLSI designs are subject to an increasingly significant thermal effect on VLSI circuit lifetime and performance variation, which can be effectively subdued by V...
We propose a new technique for hardware synthesis from higherorder functional languages with imperative features based on Reynolds's Syntactic Control of Interference. The re...
This paper presents a network architecture to interconnect mixed-signal VLSI1 integrate-and-fire neural networks in a way that the timing of the neural network data is preserved. ...