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ICC
2007
IEEE
147views Communications» more  ICC 2007»
15 years 6 months ago
VLSI Architectures for Layered Decoding for Irregular LDPC Codes of WiMax
— We present a new multi-rate architecture for decoding irregular LDPC codes in IEEE 802.16e WiMax standard. The proposed architecture utilizes the value–reuse property of offs...
Kiran K. Gunnam, Gwan S. Choi, Mark B. Yeary, Moha...
AHS
2007
IEEE
222views Hardware» more  AHS 2007»
15 years 14 days ago
Programmable Analog VLSI Architecture Based upon Event Coding
Abstract— A programmable analog array inspired from neuronal spike event coding is presented. A configurable event block forms the basic building block of the programmable array...
Thomas Jacob Koickal, Alister Hamilton, Luiz C. P....
ICCD
2007
IEEE
212views Hardware» more  ICCD 2007»
15 years 9 months ago
Analytical thermal placement for VLSI lifetime improvement and minimum performance variation
DSM and nanometer VLSI designs are subject to an increasingly significant thermal effect on VLSI circuit lifetime and performance variation, which can be effectively subdued by V...
Andrew B. Kahng, Sung-Mo Kang, Wei Li, Bao Liu
POPL
2007
ACM
16 years 19 days ago
Geometry of synthesis: a structured approach to VLSI design
We propose a new technique for hardware synthesis from higherorder functional languages with imperative features based on Reynolds's Syntactic Control of Interference. The re...
Dan R. Ghica
IWANN
2007
Springer
15 years 6 months ago
Interconnecting VLSI Spiking Neural Networks Using Isochronous Connections
This paper presents a network architecture to interconnect mixed-signal VLSI1 integrate-and-fire neural networks in a way that the timing of the neural network data is preserved. ...
Stefan Philipp, Andreas Grübl, Karlheinz Meie...