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IJCNN
2007
IEEE
15 years 6 months ago
2007
IEEE
—The paper presents a silicon neuron circuit that mimics the behaviour of known classes of biological neurons. The circuit has been designed in a 0.35µm CMOS technology. The fir...
ISCAS
2007
IEEE
15 years 6 months ago
2007
IEEE
Abstract— A low-density parity-check (LDPC) decoder architecture that supports variable block sizes and multiple code rates is presented. The proposed architecture is based on th...
76
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DT
2007
15 years 8 days ago
2007
This paper proposes a new heuristic approach to determine the input pattern that minimizes leakage currents of nanometer CMOS circuits during sleep mode considering stack and fano...
108
Voted
ENGL
2007
15 years 8 days ago
2007
— Power consumption has become a crucial concern in Built In Self Test (BIST) due to the switching activity in the circuit under test(CUT). In this paper we present a novel metho...
90
Voted
ASPDAC
2007
ACM
15 years 4 months ago
2007
ACM
Turbo decoding architectures have greater error correcting capability than any other known code. Due to their excellent performance turbo codes have been employed in several trans...