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109
Voted
GLVLSI
2007
IEEE
15 years 4 months ago
2007
IEEE
This paper describes a formal verification methodology of highnthesis (HLS) process. The abstraction level of the input to HLS is so high compared to that of the output that the v...
105
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ASPDAC
2007
ACM
15 years 4 months ago
2007
ACM
As process technology continues to scale into the nanoscale regime, interconnect plays an ever increasing role in determining VLSI system performance. As the complexity of these sy...
NIPS
2000
15 years 1 months ago
2000
Competitive learning is a technique for training classification and clustering networks. We have designed and fabricated an 11transistor primitive, that we term an automaximizing ...
ISVLSI
2007
IEEE
15 years 6 months ago
2007
IEEE
— Y -interconnects for VLSI chips are based on the use of global and semi-global wiring in only 0◦ , 60◦ , and 120◦ . Though X-interconnects are fast replacing the traditio...
106
Voted
VLSI
2007
Springer
15 years 6 months ago
2007
Springer
— Software simulation remains the most used method for VHDL RTL functional verification. The functional verification process essentially consists of two parts. The first one is t...