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89
Voted
VLSI
2007
Springer
15 years 6 months ago
2007
Springer
— In the future, high performance computing systems may consist of multiple multicore processors and reconfigurable logic coprocessors. Industry trends indicate that such coproc...
86
Voted
DFT
2007
IEEE
15 years 6 months ago
2007
IEEE
In the paper, a methodology of developing checkers for communication protocol testing is presented. It was used to develop checker to test IP cores communication protocol implemen...
78
Voted
VLSI
2007
Springer
15 years 6 months ago
2007
Springer
System design complexity is growing rapidly. As a result, current development costs are constantly increasing. It is becoming increasingly difficult to estimate how much time it ...
110
Voted
VLSI
2007
Springer
15 years 6 months ago
2007
Springer
Abstract—Analysis and verification environments for nextgeneration nano-scale RFIC designs must be able to cope with increasing design complexity and to account for new effects,...
GLVLSI
2007
IEEE
15 years 6 months ago
2007
IEEE
A PAL-based logic block is the core of great majority of contemporary CPLD devices. The purpose of the paper is to present a new approach to multi-level synthesis for PAL-based CP...