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GLVLSI
2007
IEEE
111views VLSI» more  GLVLSI 2007»
15 years 6 months ago
Probabilistic gate-level power estimation using a novel waveform set method
A probabilistic power estimation technique for combinational circuits is presented. A novel set of simple waveforms is the kernel of this technique. The transition density of each...
Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Ein...
GLVLSI
2007
IEEE
106views VLSI» more  GLVLSI 2007»
15 years 6 months ago
Floorplan repair using dynamic whitespace management
We describe an efficient, top-down strategy for overlap removal and floorplan repair which repairs overlaps in floorplans produced by placement algorithms or rough floorplanni...
Kristofer Vorwerk, Andrew A. Kennings, Doris T. Ch...
GLVLSI
2007
IEEE
189views VLSI» more  GLVLSI 2007»
15 years 6 months ago
Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems
The path-delay fault simulation of functional tests on complex circuits such as current processor-based systems is a daunting task. The amount of computing power and memory needed...
Paolo Bernardi, Michelangelo Grosso, Matteo Sonza ...
125
Voted
GLVLSI
2007
IEEE
141views VLSI» more  GLVLSI 2007»
15 years 4 months ago
A synchronization algorithm for local temporal refinements in perfectly synchronous models with nested feedback loops
he abstract and simple computation and communication mechanism in the synchronous computational model it is easy to simulate synchronous systems and to apply formal verification m...
Tarvo Raudvere, Ingo Sander, Axel Jantsch
113
Voted
GLVLSI
2007
IEEE
166views VLSI» more  GLVLSI 2007»
15 years 4 months ago
Efficient pipelining for modular multiplication architectures in prime fields
This paper presents a pipelined architecture of a modular Montgomery multiplier, which is suitable to be used in public key coprocessors. Starting from a baseline implementation o...
Nele Mentens, Kazuo Sakiyama, Bart Preneel, Ingrid...