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DFT
2007
IEEE
103views VLSI» more  DFT 2007»
15 years 6 months ago
Reliable Network-on-Chip Using a Low Cost Unequal Error Protection Code
The network-on-chip (NoC) paradigm is seen as a way of facilitating the integration of a large number of computational and storage blocks on a chip to meet several performance and...
Avijit Dutta, Nur A. Touba
DFT
2007
IEEE
142views VLSI» more  DFT 2007»
15 years 6 months ago
Quantitative Analysis of In-Field Defects in Image Sensor Arrays
Growth of pixel density and sensor array size increases the likelihood of developing in-field pixel defects. An ongoing study on defect development in imagers has now provided us ...
Jenny Leung, Jozsef Dudas, Glenn H. Chapman, Israe...
DFT
2007
IEEE
105views VLSI» more  DFT 2007»
15 years 6 months ago
A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction
Decreasing feature sizes have led to an increased vulnerability of random logic to soft errors. A particle strike may cause a glitch or single event transient (SET) at the output ...
Sybille Hellebrand, Christian G. Zoellin, Hans-Joa...
FCCM
2007
IEEE
111views VLSI» more  FCCM 2007»
15 years 6 months ago
A Structural Object Programming Model, Architecture, Chip and Tools for Reconfigurable Computing
A new platform for reconfigurable computing has an object-based programming model, with architecture, silicon and tools designed to faithfully realize this model. The platform is ...
Michael Butts, Anthony Mark Jones, Paul Wasson
FCCM
2007
IEEE
129views VLSI» more  FCCM 2007»
15 years 6 months ago
Automatic On-chip Memory Minimization for Data Reuse
FPGA-based computing engines have become a promising option for the implementation of computationally intensive applications due to high flexibility and parallelism. However, one...
Qiang Liu, George A. Constantinides, Konstantinos ...