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VLSID
2002
IEEE
91views VLSI» more  VLSID 2002»
15 years 10 months ago
Rational ABCD Modeling of High-Speed Interconnects
This paper introduces a new numerical approximation technique, called the Differential Quadrature Method (DQM), in order to derive the rational ABCD matrix representing the high-s...
Qinwei Xu, Pinaki Mazumder
VLSID
2002
IEEE
125views VLSI» more  VLSID 2002»
15 years 10 months ago
Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors
This paper shows that software pipelining can be an effective technique for code generation for coarse-grained reconfigurable instruction set processors. The paper describes a tec...
Francisco Barat, Murali Jayapala, Pieter Op de Bee...
VLSID
2002
IEEE
120views VLSI» more  VLSID 2002»
15 years 10 months ago
Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing
We describe a new algorithm for floorplan evaluation using timing-driven buffered routing according to a prescribed buffer site map. Specifically, we describe a provably good mult...
Christoph Albrecht, Andrew B. Kahng, Ion I. Mandoi...
VLSID
2002
IEEE
160views VLSI» more  VLSID 2002»
15 years 10 months ago
PREDICTMOS MOSFET Model and its Application to Submicron CMOS Inverter Delay Analysis
Predictive delay analysis is presented for a representative CMOS inverter with submicron device size using PREDICTMOS MOSFET model. As against SPICE, which adopts a time consuming...
A. B. Bhattacharyya, Shrutin Ulman
VLSID
2002
IEEE
116views VLSI» more  VLSID 2002»
15 years 10 months ago
Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization
Compare CMOS Logic with Pass-Transistor Logic, a question was raised in our mind: "Does any rule exist that contains all good?" This paper reveals novel logic synthesis ...
Kuo-Hsing Cheng, Shun-Wen Cheng