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VLSID
2006
IEEE
143views VLSI» more  VLSID 2006»
15 years 3 months ago
Frame Based Fair Multiprocessor Scheduler: A Fast Fair Algorithm for Real-Time Embedded Systems
This paper presents Frame Based Fair Multiprocessor Scheduler (FBFMS) which provides accurate real-time proportional fair scheduling for a set of dynamic tasks on a symmetric mult...
Arnab Sarkar, P. P. Chakrabarti, Rajeev Kumar
VLSID
2006
IEEE
92views VLSI» more  VLSID 2006»
15 years 9 months ago
A Wideband Frequency-Shift Keying Demodulator for Wireless Neural Stimulation Microsystems
: This paper presents a wideband frequency-shift keying (FSK) demodulator suitable for a digital data transmission chain of wireless neural stimulation microsystems such as cochlea...
Mian Dong, Chun Zhang, Songping Mai, Zhihua Wang, ...
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VLSID
2006
IEEE
240views VLSI» more  VLSID 2006»
15 years 9 months ago
An Efficient and Accurate Logarithmic Multiplier Based on Operand Decomposition
Logarithmic Number Systems (LNS) offer a viable alternative in terms of area, delay and power to binary number systems for multiplication and division operations in signal process...
Venkataraman Mahalingam, N. Ranganathan
VLSID
2006
IEEE
121views VLSI» more  VLSID 2006»
15 years 9 months ago
An Integrated Approach for Combining BDD and SAT Provers
Many formal verification tools today are based on Boolean proof techniques. The two most powerful approaches in this context are Binary Decision Diagrams (BDDs) and methods based ...
Rolf Drechsler, Görschwin Fey, Sebastian Kind...
VLSID
2006
IEEE
129views VLSI» more  VLSID 2006»
15 years 9 months ago
Modeling and Reduction of Gate Leakage during Behavioral Synthesis of NanoCMOS Circuits
For a nanoCMOS of sub-65nm technology, where the gate oxide (SiO2) thickness is very low, the gate leakage is one of the major components of power dissipation. In this paper, we pr...
Saraju P. Mohanty, Elias Kougianos