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VLSID
2007
IEEE
108views VLSI» more  VLSID 2007»
15 years 10 months ago
Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model
Accurate electrical masking modeling represents a significant challenge in soft error rate analysis for combinational logic circuits. In this paper, we use table lookup MOSFET mode...
Feng Wang 0004, Yuan Xie, R. Rajaraman, Balaji Vai...
VLSID
2007
IEEE
99views VLSI» more  VLSID 2007»
15 years 10 months ago
Low Power Implementation for Minimum Norm Sorting and Block Upper Tri-angularization of Matrices used in MIMO Wireless Systems
Multiple Input - Multiple Output (MIMO) wireless technology involves highly complex vectors and matrix computations which are directly related to increased power and area consumpt...
Zahid Khan, Tughrul Arslan, John S. Thompson, Ahme...
VLSID
2007
IEEE
103views VLSI» more  VLSID 2007»
15 years 10 months ago
Impact of Modern Process Technologies on the Electrical Parameters of Interconnects
Abstract-- This paper presents the results obtained from an experimental study of the impact of modern process technologies on the electrical parameters of interconnects. Variation...
Debjit Sinha, Jianfeng Luo, Subramanian Rajagopala...
VLSID
2007
IEEE
130views VLSI» more  VLSID 2007»
15 years 10 months ago
Memory Architecture Exploration for Power-Efficient 2D-Discrete Wavelet Transform
The Discrete Wavelet Transform (DWT) forms the core of the JPEG2000 image compression algorithm. Since the JPEG2000 compression application is heavily data-intensive, the overall ...
Rahul Jain, Preeti Ranjan Panda
VLSID
2007
IEEE
104views VLSI» more  VLSID 2007»
15 years 3 months ago
STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs
In this paper we demonstrate the impact of the floorplan on the temperature-dependent leakage power of a System on Chip (SoC). We propose a novel system level temperature aware a...
Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal...