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VLSID
2007
IEEE
142views VLSI» more  VLSID 2007»
15 years 10 months ago
Controllability-driven Power Virus Generation for Digital Circuits
The problem of peak power estimation in CMOS circuits is essential for analyzing the reliability and performance of circuits at extreme conditions. The Power Virus problem involves...
K. Najeeb, Karthik Gururaj, V. Kamakoti, Vivekanan...
VLSID
2007
IEEE
104views VLSI» more  VLSID 2007»
15 years 10 months ago
Customization of Register File Banking Architecture for Low Power
Register file banking is an effective alternative to monolithic register files in embedded processor based systems. In this work, we propose techniques for performing application s...
Rakesh Nalluri, Rohan Garg, Preeti Ranjan Panda
VLSID
2007
IEEE
100views VLSI» more  VLSID 2007»
15 years 10 months ago
Hardware Efficient Piecewise Linear Branch Predictor
Piecewise linear branch predictor has been demonstrated to have superior prediction accuracy; however, its huge hardware overhead prevents the predictor from being practical in the...
Jiajin Tu, Jian Chen, Lizy K. John
VLSID
2007
IEEE
97views VLSI» more  VLSID 2007»
15 years 10 months ago
Efficient Microprocessor Verification using Antecedent Conditioned Slicing
We present a technique for automatic verification of pipelined microprocessors using model checking. Antecedent conditioned slicing is an efficient abstraction technique for hardw...
Shobha Vasudevan, Vinod Viswanath, Jacob A. Abraha...
VLSID
2007
IEEE
152views VLSI» more  VLSID 2007»
15 years 10 months ago
An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect
With scaling of CMOS technologies, sub-threshold, gate and reverse biased junction band-to-band-tunneling leakage have increased dramatically. Together they account for more than 2...
Ashesh Rastogi, Wei Chen, Alodeep Sanyal, Sandip K...