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105
Voted
DATE
1999
IEEE
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DATE 1999
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At-Speed Boundary-Scan Interconnect Testing in a Board with Multiple System Clocks
15 years 7 months ago
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www.cecs.uci.edu
As an at-speed solution to board-level interconnect testing, an enhanced boundary-scan architecture utilizing a combination of slightly modified boundary-scan cells and a user-def...
Jongchul Shin, Hyunjin Kim, Sungho Kang
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