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    IEEEHPCS
    2010
    173views Applied Computing» more  IEEEHPCS 2010»
    Scalable instruction set simulator for thousand-core architectures running on GPGPUs
    15 years 12 days ago
    Scalable instruction set simulator for thousand-core architectures running on GPGPUs
    Download  infoscience.epfl.ch
    Simulators are still the primary tools for development and performance evaluation of applications running on massively parallel architectures. However, current virtual platforms a...
    Shivani Raghav, Martino Ruggiero, David Atienza, C...
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