Sciweavers
Explore
Publications
Books
Software
Tutorials
Presentations
Lectures Notes
Datasets
Labs
Conferences
Community
Upcoming
Conferences
Top Ranked Papers
Most Viewed Conferences
Conferences by Acronym
Conferences by Subject
Conferences by Year
Tools
PDF Tools
Image Tools
Text Tools
OCR Tools
Symbol and Emoji Tools
On-screen Keyboard
Latex Math Equation to Image
Smart IPA Phonetic Keyboard
Community
Sciweavers
About
Terms of Use
Privacy Policy
Cookies
107
Voted
PATMOS
2004
Springer
138
views
Modeling and Simulation
»
more
PATMOS 2004
»
Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic
15 years 8 months ago
Download
ce.et.tudelft.nl
The main result is the development, and delay comparison based on Logical Effort, of a number of high speed circuits for common arithmetic and related operations using threshold l...
Peter Celinski, Derek Abbott, Sorin Cotofana
claim paper
Read More »