Sciweavers

99
Voted
DAC
1997
ACM
15 years 5 months ago
Quadratic Placement Revisited
The “quadratic placement” methodology is rooted in [6] [14] [16] and is reputedly used in many commercial and in-house tools for placement of standard-cell and gate-array desi...
Charles J. Alpert, Tony F. Chan, Dennis J.-H. Huan...
98
Voted
DAC
1997
ACM
15 years 5 months ago
Data Memory Minimisation for Synchronous Data Flow Graphs Emulated on DSP-FPGA Targets
The paper presents an algorithm to determine the close-tosmallest possible data buffer sizes for arbitrary synchronous data flow (SDF) applications, such that we can guarantee the...
Marleen Adé, Rudy Lauwereins, J. A. Peperst...
123
Voted
DAC
1998
ACM
15 years 5 months ago
Global Routing with Crosstalk Constraints
—Due to the scaling down of device geometry and increasing of frequency in deep submicron designs, crosstalk between interconnection wires has become an important issue in very l...
Hai Zhou, D. F. Wong
95
Voted
DAC
1998
ACM
15 years 5 months ago
Design Methodology of Ultra Low-Power MPEG4 Codec Core Exploiting Voltage Scaling Techniques
Kimiyoshi Usami, Mutsunori Igarashi, Takashi Ishik...
DAC
1998
ACM
15 years 5 months ago
Adjoint Transient Sensitivity Computation in Piecewise Linear Simulation
This paper presents a general method for computing transient sensitivities using the adjoint method in event driven simulation algorithms that employ piecewise linear device model...
Tuyen V. Nguyen, Anirudh Devgan, Ognen J. Nastov
92
Voted
DAC
1998
ACM
15 years 5 months ago
Finite State Machine Decomposition For Low Power
José C. Monteiro, Arlindo L. Oliveira
87
Voted
DAC
1998
ACM
15 years 5 months ago
A Top-Down Design Environment for Developing Pipelined Datapaths
Robert M. McGraw, James H. Aylor, Robert H. Klenke
186
Voted
DAC
1998
ACM
15 years 5 months ago
Extending Moment Computation to 2-Port Circuit Representations
Fang-Jou Liu, Chung-Kuan Cheng
98
Voted
DAC
1998
ACM
15 years 5 months ago
Rate Optimal VLSI Design from Data Flow Graph
This paper considers the rate optimal VLSI design of a recursive data flow graph (DFG). Previous research on rate optimal scheduling is not directly applicable to VLSI design. We ...
Moonwook Oh, Soonhoi Ha
DAC
1998
ACM
15 years 5 months ago
Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions
We present a technique for synthesizing power- as well as area-optimized circuits from hierarchical data flow graphs under throughput constraints. We allow for the use of complex...
Ganesh Lakshminarayana, Niraj K. Jha