Sciweavers

72
Voted
DAC
2000
ACM
15 years 5 months ago
Maze routing with buffer insertion and wiresizing
Minghorng Lai, D. F. Wong
76
Voted
DAC
2000
ACM
15 years 5 months ago
Using general-purpose programming languages for FPGA design
ct General-purpose programming languages (GPL) are effective vehicles for FPGA design because they are easy to use, extensible, widely available, and can be used to describe both t...
Brad L. Hutchings, Brent E. Nelson
51
Voted
DAC
2000
ACM
15 years 5 months ago
Power minimization derived from architectural-usage of VLIW processors
Catherine H. Gebotys, Robert J. Gebotys, S. Wiratu...
DAC
2000
ACM
15 years 5 months ago
An asymptotically constant, linearly bounded methodology for the statistical simulation of analog circuits including component m
Abstract: This paper presents a new statistical methodology to simulate the effect of both inter-die and intra-die variation on the electrical performance of analog integrated circ...
Carlo Guardiani, Sharad Saxena, Patrick McNamara, ...
100
Voted
DAC
2000
ACM
15 years 5 months ago
Passive model order reduction of multiport distributed interconnects
Signal integrity analysis has become imperative for high-speed designs. In this paper, we present a new technique to advance Krylov-space based passive model-reduction algorithms ...
Emad Gad, Anestis Dounavis, Michel S. Nakhla, Rama...
52
Voted
DAC
2000
ACM
15 years 5 months ago
B*-Trees: a new representation for non-slicing floorplans
Yun-Chih Chang, Yao-Wen Chang, Guang-Ming Wu, Shu-...
69
Voted
DAC
2000
ACM
15 years 5 months ago
Optimizing sequential verification by retiming transformations
Gianpiero Cabodi, Stefano Quer, Fabio Somenzi
DAC
2000
ACM
15 years 5 months ago
System design of active basestations based on dynamically reconfigurable hardware
– This paper describes the system design and implementation of Active Basestations, a novel application of the run-time reconfigurable hardware technology whose applications have...
Athanassios Boulis, Mani B. Srivastava
74
Voted
DAC
2000
ACM
15 years 5 months ago
Removing user specified false paths from timing graphs
David Blaauw, Rajendran Panda, Abhijit Das