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47
Voted
ASPDAC
2010
ACM
128views Hardware» more  ASPDAC 2010»
14 years 7 months ago
Adaptive power management for real-time event streams
Kai Huang, Luca Santinelli, Jian-Jia Chen, Lothar ...
54
Voted
ASPDAC
2010
ACM
127views Hardware» more  ASPDAC 2010»
14 years 7 months ago
Data learning based diagnosis
Li-C. Wang
64
Voted
ASPDAC
2010
ACM
170views Hardware» more  ASPDAC 2010»
14 years 7 months ago
An adaptive parallel flow for power distribution network simulation using discrete Fourier transform
Xiang Hu, Wenbo Zhao, Peng Du, Amirali Shayan Aran...
67
Voted
ASPDAC
2010
ACM
125views Hardware» more  ASPDAC 2010»
14 years 7 months ago
Design and chip implementation of an instruction scheduling free ubiquitous processor
Masa-Aki Fukase, Ryosuke Murakami, Tomoaki Sato
73
Voted
ASPDAC
2010
ACM
163views Hardware» more  ASPDAC 2010»
14 years 7 months ago
A3MAP: architecture-aware analytic mapping for networks-on-chip
- In this paper, we propose a novel and global A3MAP (Architecture-Aware Analytic Mapping) algorithm applied to NoC (Networks-on-Chip) based MPSoC (Multi-Processor System-on-Chip) ...
Wooyoung Jang, David Z. Pan
42
Voted
ASPDAC
2010
ACM
133views Hardware» more  ASPDAC 2010»
14 years 7 months ago
Checker-pattern and shared two pixels LOFIC CMOS image sensors
Yoshiaki Tashiro, Shun Kawada, Shin Sakai, Shigeto...
40
Voted
ASPDAC
2010
ACM
117views Hardware» more  ASPDAC 2010»
14 years 7 months ago
Variation tolerant logic mapping for crossbar array nano architectures
Cihan Tunc, Mehdi Baradaran Tahoori
79
Voted
ASPDAC
2010
ACM
161views Hardware» more  ASPDAC 2010»
14 years 7 months ago
A dual-MST approach for clock network synthesis
Abstract--In nanometer-scale VLSI physical design, clock network becomes a major concern on determining the total performance of digital circuit. Clock skew and PVT (Process, Volta...
Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham, Evangel...
69
Voted
ASPDAC
2010
ACM
137views Hardware» more  ASPDAC 2010»
14 years 7 months ago
Managing verification error traces with bounded model debugging
Managing long verification error traces is one of the key challenges of automated debugging engines. Today, debuggers rely on the iterative logic array to model sequential behavior...
Sean Safarpour, Andreas G. Veneris, Farid N. Najm