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ISPD
2012
ACM
283views Hardware» more  ISPD 2012»
13 years 7 months ago
Low-power gated bus synthesis for 3d ic via rectilinear shortest-path steiner graph
In this paper, we propose a new approach for gated bus synthesis [16] with minimum wire capacitance per transaction in three-dimensional (3D) ICs. The 3D IC technology connects di...
Chung-Kuan Cheng, Peng Du, Andrew B. Kahng, Shih-H...
ASPDAC
2012
ACM
279views Hardware» more  ASPDAC 2012»
13 years 7 months ago
Block-level 3D IC design with through-silicon-via planning
— Since re-designing and re-optimizing existing logic, memory, and IP blocks in a 3D fashion significantly increases design cost, nearterm three-dimensional integrated circuit (...
Dae Hyun Kim, Rasit Onur Topaloglu, Sung Kyu Lim
ASPDAC
2012
ACM
334views Hardware» more  ASPDAC 2012»
13 years 7 months ago
GreenDroid: An architecture for the Dark Silicon Age
— The Dark Silicon Age kicked off with the transition to multicore and will be characterized by a wild chase for seemingly ever-more insane architectural designs. At the heart o...
Nathan Goulding-Hotta, Jack Sampson, Qiaoshi Zheng...
95
Voted
ASPDAC
2012
ACM
241views Hardware» more  ASPDAC 2012»
13 years 7 months ago
Post-fabrication reconfiguration for power-optimized tuning of optically connected multi-core systems
Abstract— Integrating optical interconnects into the nextgeneration multi-/many-core architecture has been considered a viable solution to addressing the limitations in throughpu...
Yan Zheng, Peter Lisherness, Saeed Shamshiri, Amir...
ASPDAC
2012
ACM
281views Hardware» more  ASPDAC 2012»
13 years 7 months ago
Abstract system-level models for early performance and power exploration
Andreas Gerstlauer, Suhas Chakravarty, Manan Kathu...
ASPDAC
2012
ACM
253views Hardware» more  ASPDAC 2012»
13 years 7 months ago
An integrated and automated memory optimization flow for FPGA behavioral synthesis
Behavioral synthesis tools have made significant progress in compiling high-level programs into register-transfer level (RTL) specifications. But manually rewriting code is still ...
Yuxin Wang, Peng Zhang, Xu Cheng, Jason Cong
90
Voted
ASPDAC
2012
ACM
290views Hardware» more  ASPDAC 2012»
13 years 7 months ago
CODA: A concurrent online delay measurement architecture for critical paths
With technology scaling, integrated circuits behave more unpredictably due to process variation, environmental changes and aging effects. Various variation-aware and adaptive desi...
Yubin Zhang, Haile Yu, Qiang Xu
ASPDAC
2012
ACM
241views Hardware» more  ASPDAC 2012»
13 years 7 months ago
On error modeling of electrical bugs for post-silicon timing validation
—There is great demand for an accurate and scalable metric to evaluate the functional stimuli, testbench checkers, and DfD (Design-for-Debug) structures used in post-silicon timi...
Ming Gao, Peter Lisherness, Kwang-Ting Cheng, Jing...
ASPDAC
2012
ACM
265views Hardware» more  ASPDAC 2012»
13 years 7 months ago
Improving validation coverage metrics to account for limited observability
—In both pre-silicon and post-silicon validation, the detection of design errors requires both stimulus capable of activating the errors and checkers capable of detecting the beh...
Peter Lisherness, Kwang-Ting Cheng
ASPDAC
2012
ACM
247views Hardware» more  ASPDAC 2012»
13 years 7 months ago
Through-silicon-via-induced obstacle-aware clock tree synthesis for 3D ICs
— In this paper, we present an obstacle-aware clock tree synthesis method for through-silicon-via (TSV)-based 3D ICs. A unique aspect of this problem lies in the fact that variou...
Xin Zhao, Sung Kyu Lim