ISCA
2005
IEEE
15 years 3 months ago
2005
IEEE
Pipelined forwarding engines are used in core routers to meet speed demands. Tree-based searches are pipelined across a number of stages to achieve high throughput, but this resul...
IPPS
2005
IEEE
15 years 3 months ago
2005
IEEE
In this paper, we propose an IPSec implementation on Xilinx Virtex-II Pro FPGA1 . We move the key management and negotiation into software function calls that run on the PowerPC p...
114
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IEEEPACT
2005
IEEE
15 years 3 months ago
2005
IEEE
Current integration trends embrace the prosperity of single-chip multi-core processors. Although multi-core processors deliver significantly improved system throughput, single-thr...
102
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IEEEPACT
2005
IEEE
15 years 3 months ago
2005
IEEE
VLIW architectures are popular in embedded systems because they offer high-performance processing at low cost and energy. The major problem with traditional VLIW designs is that t...
IEEEPACT
2005
IEEE
15 years 3 months ago
2005
IEEE
Dynamic optimization has the potential to adapt the program’s behavior at run-time to deliver performance improvements over static optimization. Dynamic optimization systems usu...
IEEEPACT
2005
IEEE
15 years 3 months ago
2005
IEEE
While general-purpose processors have only recently employed chip multiprocessor (CMP) architectures, network processors (NPs) have used heterogeneous multi-core architectures sin...
IEEEPACT
2005
IEEE
15 years 3 months ago
2005
IEEE
Coherence misses in shared-memory multiprocessors account for a substantial fraction of execution time in many important scientific and commercial workloads. Memory streaming prov...
IEEEPACT
2005
IEEE
15 years 3 months ago
2005
IEEE
We describe the design, generation and compression of the extended whole program path (eWPP) representation that not only captures the control flow history of a program execution...
IEEEPACT
2005
IEEE
15 years 3 months ago
2005
IEEE
llel Abstractions in Fortress Guy Steele Sun Microsystems Laboratories April 24, 2006
86
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IEEEPACT
2005
IEEE
15 years 3 months ago
2005
IEEE
Helper threading is a technique that utilizes a second core or logical processor in a multi-threaded system to improve the performance of the main thread. A helper thread executes...