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    GLVLSI
    1996
    IEEE
    102views VLSI» more  GLVLSI 1996»
    FPGA-based high performance page layout segmentation
    13 years 10 months ago
    FPGA-based high performance page layout segmentation
    Download  www.cecs.uci.edu
    Nalini K. Ratha, Anil K. Jain, Diane T. Rover
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    GLVLSI
    1996
    IEEE
    103views VLSI» more  GLVLSI 1996»
    A Parametrical Architecture for Reed-Solomon Decoders
    13 years 10 months ago
    A Parametrical Architecture for Reed-Solomon Decoders
    Download  www.cs.york.ac.uk
    Mariana-Eugenia Petre, Guido Masera
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    GLVLSI
    1996
    IEEE
    77views VLSI» more  GLVLSI 1996»
    A Parameterized Index-Generator for the Multi-Dimensional Interleaving Optimization
    13 years 10 months ago
    A Parameterized Index-Generator for the Multi-Dimensional Interleaving Optimization
    Download  www.cecs.uci.edu
    Nelson L. Passos, Edwin Hsing-Mean Sha
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    GLVLSI
    1996
    IEEE
    91views VLSI» more  GLVLSI 1996»
    Macromodeling C- and RC-loaded CMOS inverters for timing analysis
    13 years 10 months ago
    Macromodeling C- and RC-loaded CMOS inverters for timing analysis
    Download  www.cecs.uci.edu
    Ayman I. Kayssi
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    GLVLSI
    1996
    IEEE
    109views VLSI» more  GLVLSI 1996»
    Least Upper Bounds on the Sizes of Symmetric Variable Order based OBDDs
    13 years 10 months ago
    Least Upper Bounds on the Sizes of Symmetric Variable Order based OBDDs
    Download  www.cecs.uci.edu
    Laura Heinrich-Litan, Paul Molitor, Dirk Möll...
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    GLVLSI
    1996
    IEEE
    96views VLSI» more  GLVLSI 1996»
    A Provably Good Moat Routing Algorithm
    13 years 10 months ago
    A Provably Good Moat Routing Algorithm
    Download  www.cecs.uci.edu
    Joseph L. Ganley, James P. Cohoon
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    GLVLSI
    1996
    IEEE
    139views VLSI» more  GLVLSI 1996»
    Design and VLSI Implementation of a Unified Synapse-Neuron Architecture
    13 years 10 months ago
    Design and VLSI Implementation of a Unified Synapse-Neuron Architecture
    Download  www.cecs.uci.edu
    Hormoz Djahanshahi, Majid Ahmadi, Graham A. Jullie...
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    GLVLSI
    1996
    IEEE
    115views VLSI» more  GLVLSI 1996»
    A VLSI Interconnection Network Router Using a D-CAM with Hidden Refresh
    13 years 10 months ago
    A VLSI Interconnection Network Router Using a D-CAM with Hidden Refresh
    Download  www.eecs.wsu.edu
    A VLSI implementation of a programmable router schemefor parallel interconnectionnetwork architectures is presented in this paper. The router executes routing
    José G. Delgado-Frias, Jabulani Nyathi, Che...
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    GLVLSI
    1996
    IEEE
    145views VLSI» more  GLVLSI 1996»
    Boolean Function Representation Using Parallel-Access Diagrams
    13 years 10 months ago
    Boolean Function Representation Using Parallel-Access Diagrams
    Download  www.eecs.umich.edu
    Inthispaperweintroduceanondeterministiccounterpart to Reduced, Ordered Binary Decision Diagrams for the representation and manipulation of logic functions. ROBDDs are conceptually...
    Valeria Bertacco, Maurizio Damiani
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    GLVLSI
    1996
    IEEE
    86views VLSI» more  GLVLSI 1996»
    A Reprogrammable FPGA-Based ATM Traffic Generator
    13 years 10 months ago
    A Reprogrammable FPGA-Based ATM Traffic Generator
    Download  www.cecs.uci.edu
    Pong P. Chu
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